1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a static semiconductor memory device having high resistance load type memory cells.
2. Description of the Background Art
FIG. 8 is a block diagram showing exemplary structure of a general static random access memory (hereinafter referred to as "static RAM").
Referring to FIG. 8, a memory cell array 100 is formed by a plurality of word lines and a plurality of bit line pairs, which are arranged to intersect with each other, and memory cells provided on the intersections thereof. A row address buffer 101 amplifies or inverts an externally applied row address signal RA, to supply the same to a row decoder 102. The row decoder 102 decodes the row address signal RA, to select one of the plurality of wcrd lines provided in the memory cell array 100. A column address buffer 103 amplifies or inverts an externally applied column address signal CA, to supply the same to a column decoder 104. The column decoder 104 decodes the column address signal CA, to select one of the plurality of bit line pairs provided in the memory cell array 100. A multiplexer 105 connects the selected bit line pair to a sense amplifier 108 through an input/output line pair.
A read/write control circuit 106 controls a data input buffer 107, the sense amplifier 108 and a data output buffer 109 in response to a chip selection signal CS and a write signal WE, which are supplied from the exterior. In data writing, the data input buffer 107 amplifies externally supplied input data D.sub.in, to supply the same to the multiplexer 105. In data reading, the sense amplifier 108 senses and amplifies a read voltage of a small amplitude which is read from the memory cell array 100. The data output buffer 109 further amplifies the level of the output from the sense amplifier 108, to output the same to the exterior as output data D.sub.out.
FIG. 9 illustrates the structure of the memory cell array 100 in detail. In order to simplify the illustration, FIG. 9 shows only a two-by-two array of memory cells.
As shown in FIG. 9, a plurality of bit line pairs BL and BL and a plurality of word lines WL are arranged to intersect with each other, while memory cells MC1 to MC4 are provided on the intersections. The bit line pairs BL and BL are connected to an input/output line pair I/O and I/O through a plurality of transfer gates 23 and 24, which form the multiplexer 105 shown in FIG. 8. Further, the bit line pairs BL and BL are coupled to a source potential V.sub.CC through bit line loading transistors 21 and 22. Outputs from the row decoder 102 are supplied to the word lines WL, while outputs Y.sub.1 and Y.sub.2 of the column decoder 104 are supplied to the transfer gates 23 and 24.
Each of the memory cells MC1 to MC4 is formed of a high resistance/load type NMOS memory cell shown in FIG. 11, or a CMOS memory cell shown in FIG. 11, for example.
Referring to FIG. 10, a driver transistor 11 is coupled between a storage node N1 and the ground potential, while another driver transistor 12 is coupled between another storage node N2 and the ground potential. The gate of the driver transistor 11 is connected to the storage node N2, while the gate of the driver transistor 12 is connected to the storage node N1. An access transistor 13 is connected between a bit line BL and the storage node N1, while another transistor 14 is connected between another bit line BL and the storage node N2. The gates of the access transistors 13 and 14 are connected to a word line WL. Further, a load resistance 15 is coupled between a source potential V.sub.CC and the storage node Nl, while another load resistance 16 is coupled between the source potential V.sub.CC and the storage node N2.
The transistors 11 to 14 are formed of N-channel MOSFETs, and the load resistances 15 and 16 have high resistance values. The driver transistors 11 and 12 and the load resistances 15 and 16 form a flip-flop. The storage nodes N1 and N2 store data which are complementary to each other. The access transistors 13 and 14 serve as transfer gates between the memory cell and the bit lines BL and BL.
The memory cell shown in FIG. 11 is provided with P-channel MOSFETs 17 and 18, in place of the load resistances 15 and 16 shown in FIG. 10.
The operation of the static RAM shown in FIGS. 8 to 10 will now be described.
In response to the row address signal RA, the row decoder 102 selects one of the plurality of word lines WL to raise up its potential to a high level, while bringing potentials of the remaining word lines WL into low levels. In response to the column address signal CA, the column decoder 104 selects one of the plurality of bit line pairs BL and BL to allow conduction of the transfer gates 23 and 24 corresponding to the selected bit line pair BL and BL. Thus, only the selected pair of bit lines BL and BL are connected to the input/output line pair I/O and I/O, while the remaining non-selected bit line pairs BL and BL are cut off from the input/output line pair I/O and I/O. Thus, selected is the memory cell, which is located on the intersection between the selected word line and the selected bit line pair BL and BL. When the memory cell MC1 is selected, for example, the remaining memory cells MC2 to MC4 are in non-selected states.
The operation of the selected memory cell will now be described with reference to FIGS. 10, 12 and 13.
Referring to FIGS. 10 and 12, read operation of the selected memory cell is first described. It is assumed here that the storage node N1 stores data of "H" and the storage node N2 stores data of "L". At this time, the driver transistor 11 is in a nonconducting state, and the driver transistor 12 is in a conducting state.
When a word line WL corresponding to an address An + 1 is selected and its potential goes high, both of the access transistors 13 and 14 enter conducting states. Thus, a direct current flows through a path of a power terminal, the bit line loading transistor 22 (FIG. 9), the bit line BL, the access transistor 14, the driver transistor 12 and an earth terminal. On the other hand, no direct current flows through a path of a power terminal, the bit line loading transistor 21 (FIG. 9), the bit line BL, the access transistor 13, the driver transistor 11 and an earth terminal since the driver transistor 11 is in the nonconducting state.
In this case, the bit line BL carrying no direct current has a potential which is lower than the source potential V.sub.CC by a threshold voltage V.sub.th of the bit line loading transistor 21 (FIG. 9). The bit line BL carrying the direct current has a potential which is determined by resistance partial pressure caused by ON resistances of the bit line loading transistor 22 (FIG. 9), the access transistor 14 and the driver transistor 12. This potential is lower than the source potential V.sub.CC by the threshold voltage V.sub.th and a prescribed voltage .DELTA.V of about 50 to 500 mV in general. This voltage .DELTA.V, which is called a bit line amplitude, is adjusted by the bit line loading transistor 22.
This bit line amplitude appears on the input/output line pair I/O and I/O through the transfer gates 23 and 24. The bit line amplitude is amplified by the sense amplifier 108, further amplified by the output buffer 109, and read out to the exterior as the output data D.sub.out (see FIG. 9). In the data read operation, the read/write control circuit 106 (FIG. 8) controls the data input buffer 107, not to drive the input/output line pair I/O and I/O.
With reference to FIGS. 10 and 13, write operation of the selected memory cell will now be described. It is assumed here that data of "L" is written in the storage node Nl and data of "H" is written in the storage node N2.
In this case, the data input buffer 107 brings the potentials of the input/output lines I/O and I/O into low and high levels respectively (see FIG. 9). Thus, the potential of the bit line BL goes low and that of the bit line BL goes high. Consequently, the potentials of the storage nodes N1 and N2 go low and high respectively within the memory cell corresponding to the address An + 1. As shown in FIG. 13, this write operation is performed when the write signal WE goes low.
With reference to the aforementioned static RAM, the characteristics of a non-selected memory cell will now be described.
When the potential of the storage node N1 is at a high level (source potential V.sub.CC) in FIG. 10, the driver transistor 12 is in an ON state. Thus, the storage node N2 is connected to the ground potential through the ON resistance of the driver transistor 12. Since the load resistance 16 has an extremely high resistance value, the potential of the storage node N2 is equal to the ground potential. Since the potential of the storage node N2 is thus equal to the ground potential, the driver transistor 11 is in an OFF state. Therefore, the storage node N1 is charged substantially at the level of the source potential V.sub.CC through the load resistance 15. However, even if a gate voltage is 0 V, a fine leakage current, i.e., a subthreshold current flows in the MOSFET. Therefore, the driver transistor 11 has a finite OFF resistance even if the same is in an OFF state.
In such a static RAM, the current in its standby state is limited along standards. Therefore, it is necessary to increase the resistance values of the load resistances 15 and 16 as the storage capacity is increased. In the case of a 4-MB static RAM, it is necessary to use load resistances having extremely high resistance values of about 10 T.OMEGA. (teraohm).
An OFF resistance value of a transistor is defined here by a source-to-drain resistance value which is obtained when the transistor has a gate-to-source voltage of 0 V. The potential of the storage node Nl is determined by the resistive divisional ratio of the resistance value of the load resistance 15 to the OFF resistance value of the driver transistor 11. Thus, the storage node N1 cannot be maintained at a high potential when the resistance value of the load resistance 15 is increased. Therefore, it is necessary to set the OFF resistance values of the driver transistors 11 and 12 to be larger than the resistance values of the load resistances 15 and 16.
FIG. 14 shows the relation between a gate voltage V.sub.G of a MOSFET and a subthreshold current I.sub.d. As shown in FIG. 14, the subthreshold current I.sub.d is reduced by about one place as the gate voltage V.sub.G is reduced by 0.1 V. For example, a threshold voltage V.sub.th is defined by the gate voltage V.sub.G obtained when the subthreshold current I.sub.d is 1 .times.10.sup.-6 A. If the threshold voltage V.sub.th is increased, the curve shown in FIG. 14 is rightwardly shifted to reduce the current (OFF current) which is obtained when the gate voltage V.sub.G is 0 V. The OFF resistance value is evaluated by dividing a drain voltage by an OFF current, and hence the OFF resistance value is increased by about one place when the threshold voltage V.sub.th is increased by 0.1 V.
Thus, when the resistance values of the load resistances 15 and 16 are increased, the resistance values of the driver transistors 11 and 12 may unavoidably become smaller than those of the load resistances 15 and 16, if the transistors of the memory cell have low threshold voltages V.sub.th. In this case, there is such possibility that the storage node N1 cannot hold a potential close to the source potential V.sub.CC, and the data stored in the storage nodes N1 and N2 may be inverted.
The characteristics of a selected memory cell will now be described. FIG. 15 shows the relation (transfer characteristics) between the potentials of the storage nodes N1 and N2 of the selected memory cell.
The potentials of the storage nodes N1 and N2 are stabilized at two points A and B. When the potential of the word line WL goes high in FIG. 10, the potential of the storage node N2 is weakly pulled up by the bit line loading transistor 22 (FIG. 9) through the access transistor 14. Therefore, the potential of the storage node N2 is slightly higher than the ground potential. Thus, the OFF resistance value of the driver transistor 11 is smaller than the resistance value of the load resistance 15, whereby the leakage current flowing in the driver transistor 11 is increased. Consequently, the potential of the storage node N1 is reduced. However, when the potential of the storage node N1 is reduced to a level lower than the source potential V.sub.CC by the threshold voltage V.sub.th, the access transistor 13 is turned on. Thus, the storage node N1 is charged by the bit line loading transistor 21 (FIG. 9) through the access transistor 13, and hence the potential of the storage node N1 will not be reduced beyond V.sub.H.
Referring to FIG. 15, the size of a circle a enclosed by two curves expressing the potentials of the storage nodes N1 and N2 serves as an index showing stability of the selected memory cell. When the circle a is large the memory cell can stably hold the data. When the threshold voltages of the transistors forming the memory cell are increased, the circle a is reduced in size and stability of the memory cell is deteriorated.
Thus, the transistors forming the memory cell preferably have high threshold voltages V.sub.th for holding the data in a non-selected state. However, the transistors preferably have low threshold voltages V.sub.th in order to ensure stability of the memory cell in a selected state. It is difficult to satisfy such inconsistent requirements as the resistance values of the load resistances are increased.